A computing system may have a main memory that is randomly accessed over a memory channel a single address at a time per memory transaction. Sometimes a data bus in a memory channel of the main memory may be idle waiting for the next address and memory transaction to occur. The idle time can lower the data bandwidth of a memory channel.
With low latency memory modules, the data bandwidth of a memory channel lost from idle time is less significant. However if memory modules with a higher latency or a variable latency are introduced into the main memory, the data bandwidth loss may become more significant.